Update README for ascad-v2-1 with dimensions and leakage plots

README.md

@@ -73,7 +73,9 @@ This dataset is stored in Zarr format, optimized for chunked and compressed clou
 | ascad-v2-1 | `v2_hd_perm_pointer_transition` | 0 | <details><summary>View</summary>HD(perm[byte_index], perm[(byte_index - 1) % 16])<br><br>Models the CPU address register or general-purpose register updating  from the previous physical byte offset to the current physical byte offset.</details> | <img src="plots/ascad_v2_1_v2_hd_perm_pointer_transition_0.png" alt="ascad-v2-1 v2_hd_perm_pointer_transition" width="600"/> | <img src="plots/ascad_v2_1_v2_hd_perm_pointer_transition_0_zoomed.png" alt="Zoomed v2_hd_perm_pointer_transition" width="400"/> |
 | ascad-v2-1 | `v2_hd_ptx_key` | 0 | <details><summary>View</summary>HD between rm*ptx[j] and rm*key[j] where ``j = perm[byte_index]``.</details> | <img src="plots/ascad_v2_1_v2_hd_ptx_key_0.png" alt="ascad-v2-1 v2_hd_ptx_key" width="600"/> | <img src="plots/ascad_v2_1_v2_hd_ptx_key_0_zoomed.png" alt="Zoomed v2_hd_ptx_key" width="400"/> |
 | ascad-v2-1 | `v2_hd_ptx_sbi` | 0 | <details><summary>View</summary>HD between the unmasked plaintext and the unmasked SBI.<br><br>``HD(ptx[j], ptx[j] ^ key[j])``  where  ``j = perm[byte_index]``.</details> | <img src="plots/ascad_v2_1_v2_hd_ptx_sbi_0.png" alt="ascad-v2-1 v2_hd_ptx_sbi" width="600"/> | <img src="plots/ascad_v2_1_v2_hd_ptx_sbi_0_zoomed.png" alt="Zoomed v2_hd_ptx_sbi" width="400"/> |
+| ascad-v2-1 | `v2_hd_rin_to_rout_load` | 0 | <details><summary>View</summary>HD between the global boolean masks rin and rout.<br><br>``HD(rin, rout)``. These are loaded back-to-back from the random buffer T_rand (indices 16 and 17) during aes_init_enc. This directly targets the memory data bus transition  at the very start of the trace.</details> | <img src="plots/ascad_v2_1_v2_hd_rin_to_rout_load_0.png" alt="ascad-v2-1 v2_hd_rin_to_rout_load" width="600"/> | <img src="plots/ascad_v2_1_v2_hd_rin_to_rout_load_0_zoomed.png" alt="Zoomed v2_hd_rin_to_rout_load" width="400"/> |
 | ascad-v2-1 | `v2_hd_rm_rm_sbi` | 0 | <details><summary>View</summary>HD(rm, rm * (ptx[j] ^ key[j])) where j = perm[byte_index]. Models the hardware register transition from the multiplicative mask to the multiplicatively masked SBI.</details> | <img src="plots/ascad_v2_1_v2_hd_rm_rm_sbi_0.png" alt="ascad-v2-1 v2_hd_rm_rm_sbi" width="600"/> | - |
+| ascad-v2-1 | `v2_hd_rmult_to_inv_log` | 0 | <details><summary>View</summary>HD between the multiplicative mask and its inverse log.<br><br>``HD(rmult, 255 - LOG[rmult])``. Models the Cortex-M4 ALU transitioning from holding the raw multiplicative  mask to computing its inverse log for the final ciphertext division.</details> | <img src="plots/ascad_v2_1_v2_hd_rmult_to_inv_log_0.png" alt="ascad-v2-1 v2_hd_rmult_to_inv_log" width="600"/> | <img src="plots/ascad_v2_1_v2_hd_rmult_to_inv_log_0_zoomed.png" alt="Zoomed v2_hd_rmult_to_inv_log" width="400"/> |
 | ascad-v2-1 | `v2_hd_rout_mask_interaction` | 0 | <details><summary>View</summary>Hamming distance between the global rout mask and the per-byte mask.<br><br>``HD(rout, mask[j])``  where  ``j = perm[byte_index]``.</details> | <img src="plots/ascad_v2_1_v2_hd_rout_mask_interaction_0.png" alt="ascad-v2-1 v2_hd_rout_mask_interaction" width="600"/> | <img src="plots/ascad_v2_1_v2_hd_rout_mask_interaction_0_zoomed.png" alt="Zoomed v2_hd_rout_mask_interaction" width="400"/> |
 | ascad-v2-1 | `v2_hd_rout_raw_out` | 0 | <details><summary>View</summary>HD(rout, rm * SBOX(ptx[j] ^ key[j]) ^ rout) where j = perm[byte_index]. Models the transition between the global output mask and the raw LUT output.</details> | <img src="plots/ascad_v2_1_v2_hd_rout_raw_out_0.png" alt="ascad-v2-1 v2_hd_rout_raw_out" width="600"/> | - |
 | ascad-v2-1 | `v2_hd_rout_sbo_mid` | 0 | <details><summary>View</summary>HD(rout, rm * SBOX(ptx[j] ^ key[j]) ^ rout ^ mask[j]) where j = perm[byte_index]. Models the transition from the global output mask to the state inside the SubBytes inner loop  after the per-byte mask has been added, but before rout is stripped.</details> | <img src="plots/ascad_v2_1_v2_hd_rout_sbo_mid_0.png" alt="ascad-v2-1 v2_hd_rout_sbo_mid" width="600"/> | <img src="plots/ascad_v2_1_v2_hd_rout_sbo_mid_0_zoomed.png" alt="Zoomed v2_hd_rout_sbo_mid" width="400"/> |
@@ -81,6 +83,7 @@ This dataset is stored in Zarr format, optimized for chunked and compressed clou
 | ascad-v2-1 | `v2_hd_sbi_sbo` | 0 | <details><summary>View</summary>HD between the unmasked SBI and unmasked SBO.<br><br>``HD(ptx[j] ^ key[j], SBOX(ptx[j] ^ key[j]))``  where  ``j = perm[byte_index]``.</details> | <img src="plots/ascad_v2_1_v2_hd_sbi_sbo_0.png" alt="ascad-v2-1 v2_hd_sbi_sbo" width="600"/> | - |
 | ascad-v2-1 | `v2_hd_sbo_affine_mc` | 0 | <details><summary>View</summary>HD between the affine SBO and the masked MixColumns output.<br><br>``HD(rm*SBOX(ptx[j]^key[j])^mask[j], MixColumns(...)[j])`` where ``j = perm[byte_index]``.</details> | <img src="plots/ascad_v2_1_v2_hd_sbo_affine_mc_0.png" alt="ascad-v2-1 v2_hd_sbo_affine_mc" width="600"/> | - |
 | ascad-v2-1 | `v2_hd_sbo_mid_to_mask` | 0 | <details><summary>View</summary>HD(rm * SBOX(...) ^ rout ^ mask[j], mask[j]) where j = perm[byte_index].<br><br>Models the power dissipation in the ALU as the heavily masked intermediate  state interacts with the pure per-byte additive mask.</details> | <img src="plots/ascad_v2_1_v2_hd_sbo_mid_to_mask_0.png" alt="ascad-v2-1 v2_hd_sbo_mid_to_mask" width="600"/> | <img src="plots/ascad_v2_1_v2_hd_sbo_mid_to_mask_0_zoomed.png" alt="Zoomed v2_hd_sbo_mid_to_mask" width="400"/> |
+| ascad-v2-1 | `v2_hd_shiftrows_decorrelation` | 0 | <details><summary>View</summary>HD between the state byte and mask byte processed at the same loop index.<br><br>``HD(state[j], mask[k])`` where ``j = perm[i]`` and ``k = perm_bis[i]``. Because the firmware uses two sequential loops of 16 for ShiftRows,  there is often physical pipeline cross-talk between the loop iterations.</details> | <img src="plots/ascad_v2_1_v2_hd_shiftrows_decorrelation_0.png" alt="ascad-v2-1 v2_hd_shiftrows_decorrelation" width="600"/> | <img src="plots/ascad_v2_1_v2_hd_shiftrows_decorrelation_0_zoomed.png" alt="Zoomed v2_hd_shiftrows_decorrelation" width="400"/> |
 | ascad-v2-1 | `v2_hd_unmasked_sbi_bus` | 0 | <details><summary>View</summary>HD(ptx[j] ^ key[j], ptx[prev_j] ^ key[prev_j]) where j = perm[byte_index] and prev_j = perm[(byte_index - 1) % 16].<br><br>Models the memory data bus sequentially carrying the unmasked S-Box Inputs  as the firmware loops through the permuted byte indices.</details> | <img src="plots/ascad_v2_1_v2_hd_unmasked_sbi_bus_0.png" alt="ascad-v2-1 v2_hd_unmasked_sbi_bus" width="600"/> | - |
 | ascad-v2-1 | `v2_hd_unmasked_sbo_bus` | 0 | <details><summary>View</summary>HD(SBOX(ptx[j] ^ key[j]), SBOX(ptx[prev_j] ^ key[prev_j])) where j = perm[byte_index] and prev_j = perm[(byte_index - 1) % 16].<br><br>Models the memory data bus sequentially reading or writing the unmasked  S-Box Outputs back to RAM during a permuted loop.</details> | <img src="plots/ascad_v2_1_v2_hd_unmasked_sbo_bus_0.png" alt="ascad-v2-1 v2_hd_unmasked_sbo_bus" width="600"/> | <img src="plots/ascad_v2_1_v2_hd_unmasked_sbo_bus_0_zoomed.png" alt="Zoomed v2_hd_unmasked_sbo_bus" width="400"/> |
 | ascad-v2-1 | `v2_hd_unmasked_sbo_to_parity` | 0 | <details><summary>View</summary>HD(SBOX(ptx[j] ^ key[j]), SBOX(sbi_0) ^ SBOX(sbi_1) ^ SBOX(sbi_2) ^ SBOX(sbi_3)) where j = perm[byte_index].<br><br>Models the ALU transitioning from holding a single unmasked column byte  to holding the fully XOR'd parity variable for that column during MixColumns.</details> | <img src="plots/ascad_v2_1_v2_hd_unmasked_sbo_to_parity_0.png" alt="ascad-v2-1 v2_hd_unmasked_sbo_to_parity" width="600"/> | - |
@@ -116,6 +119,7 @@ This dataset is stored in Zarr format, optimized for chunked and compressed clou
 | ascad-v2-1 | `v2_id_bitwise_not_ptx` | 0 | <details><summary>View</summary>256-class Identity target for the logical NOT of the Plaintext.<br><br>``(~ptx[j]) & 0xFF`` where ``j = perm[byte_index]``. Useful for modeling power dissipation when the raw plaintext is drained  from the data bus or overwritten by its complement.</details> | <img src="plots/ascad_v2_1_v2_id_bitwise_not_ptx_0.png" alt="ascad-v2-1 v2_id_bitwise_not_ptx" width="600"/> | - |
 | ascad-v2-1 | `v2_id_bitwise_or_ptx_key` | 0 | <details><summary>View</summary>256-class Identity target for the bitwise OR of Plaintext and Key.<br><br>``(ptx[j] | key[j])`` where ``j = perm[byte_index]``. Models the physical state where bus lines might be driven high by either  operand during concurrent fetch or pipeline stalling.</details> | <img src="plots/ascad_v2_1_v2_id_bitwise_or_ptx_key_0.png" alt="ascad-v2-1 v2_id_bitwise_or_ptx_key" width="600"/> | <img src="plots/ascad_v2_1_v2_id_bitwise_or_ptx_key_0_zoomed.png" alt="Zoomed v2_id_bitwise_or_ptx_key" width="400"/> |
 | ascad-v2-1 | `v2_id_bitwise_xnor_ptx_key` | 0 | <details><summary>View</summary>256-class Identity target for the bitwise XNOR of Plaintext and Key.<br><br>``~(ptx[j] ^ key[j]) & 0xFF`` where ``j = perm[byte_index]``. The logical inverse of the S-Box Input. Identifies leakage specific to  inverted bus logic or pre-charge-to-1 memory architectures on the STM32.</details> | <img src="plots/ascad_v2_1_v2_id_bitwise_xnor_ptx_key_0.png" alt="ascad-v2-1 v2_id_bitwise_xnor_ptx_key" width="600"/> | - |
+| ascad-v2-1 | `v2_id_inv_log_rmult` | 0 | <details><summary>View</summary>256-class Identity target for the inverse log of the multiplicative mask.<br><br>``ID( (255 - LOG[rmult]) mod 255 )``. Used inside Multiplicative_unmasking at the very end of Round 10 to do  a constant-time GF(256) division to recover the raw ciphertext.</details> | <img src="plots/ascad_v2_1_v2_id_inv_log_rmult_0.png" alt="ascad-v2-1 v2_id_inv_log_rmult" width="600"/> | <img src="plots/ascad_v2_1_v2_id_inv_log_rmult_0_zoomed.png" alt="Zoomed v2_id_inv_log_rmult" width="400"/> |
 | ascad-v2-1 | `v2_id_keyschedule_sbox` | 0 | <details><summary>View</summary>256-class Identity target for the Key Expansion SubWord operation.<br><br>``SBOX(key[byte_index])``. During the generation of Round Key 1, specific key bytes (12, 13, 14, 15)  are pushed through the S-Box. This provides a pure, unmasked target that  is completely uncoupled from the plaintext or masking scheme.</details> | <img src="plots/ascad_v2_1_v2_id_keyschedule_sbox_0.png" alt="ascad-v2-1 v2_id_keyschedule_sbox" width="600"/> | <img src="plots/ascad_v2_1_v2_id_keyschedule_sbox_0_zoomed.png" alt="Zoomed v2_id_keyschedule_sbox" width="400"/> |
 | ascad-v2-1 | `v2_id_linear_add_ptx_key` | 0 | <details><summary>View</summary>256-class Identity target for the Arithmetic Addition of Plaintext and Key.<br><br>``(ptx[i] + key[i]) mod 256`` where ``i = byte_index`` (Linear order). While AES uses logical XOR, the Cortex-M4 ALU shares silicon for ADD and EOR.  Targeting arithmetic addition forces the DL model to capture physical  carry-chain and borrow-chain leakage propagating through the ALU circuitry.</details> | <img src="plots/ascad_v2_1_v2_id_linear_add_ptx_key_0.png" alt="ascad-v2-1 v2_id_linear_add_ptx_key" width="600"/> | - |
 | ascad-v2-1 | `v2_id_masked_sbi` | 0 | <details><summary>View</summary>256-class Identity target for the affine-masked SBI. Passes the exact byte value directly to the DL model.</details> | <img src="plots/ascad_v2_1_v2_id_masked_sbi_0.png" alt="ascad-v2-1 v2_id_masked_sbi" width="600"/> | <img src="plots/ascad_v2_1_v2_id_masked_sbi_0_zoomed.png" alt="Zoomed v2_id_masked_sbi" width="400"/> |
@@ -130,6 +134,7 @@ This dataset is stored in Zarr format, optimized for chunked and compressed clou
 | ascad-v2-1 | `v2_id_rin_rout_interaction` | 0 | <details><summary>View</summary>256-class Identity target for the interaction of the two global Boolean masks.<br><br>``ID(rin ^ rout)``. These are loaded from memory simultaneously and baked into the sboxMasked  LUT together. Their combined state frequently creates a stable baseline leakage.</details> | <img src="plots/ascad_v2_1_v2_id_rin_rout_interaction_0.png" alt="ascad-v2-1 v2_id_rin_rout_interaction" width="600"/> | <img src="plots/ascad_v2_1_v2_id_rin_rout_interaction_0_zoomed.png" alt="Zoomed v2_id_rin_rout_interaction" width="400"/> |
 | ascad-v2-1 | `v2_id_sbo_affine` | 0 | <details><summary>View</summary>256-class Identity target for the affine-masked SBO (post-rout strip). Passes the exact byte value directly to the DL model.</details> | <img src="plots/ascad_v2_1_v2_id_sbo_affine_0.png" alt="ascad-v2-1 v2_id_sbo_affine" width="600"/> | <img src="plots/ascad_v2_1_v2_id_sbo_affine_0_zoomed.png" alt="Zoomed v2_id_sbo_affine" width="400"/> |
 | ascad-v2-1 | `v2_id_shifted_unmasked_sbo` | 0 | <details><summary>View</summary>256-class Identity target for the unmasked state byte AFTER ShiftRows.<br><br>``SBOX(ptx[source_j] ^ key[source_j])`` where ``source_j`` physically shifts into ``perm[byte_index]``. Forces the deep learning model to track the unmasked byte across the spatial permutation.</details> | <img src="plots/ascad_v2_1_v2_id_shifted_unmasked_sbo_0.png" alt="ascad-v2-1 v2_id_shifted_unmasked_sbo" width="600"/> | - |
+| ascad-v2-1 | `v2_id_shiftrows_mask_bis` | 0 | <details><summary>View</summary>256-class Identity target for the mask byte accessed during ShiftRows.<br><br>``ID(mask[k])`` where ``k = perm_indices_bis[byte_index]``. Models the memory bus fetching the additive mask during the completely  decorrelated state2 ShiftRows loop.</details> | <img src="plots/ascad_v2_1_v2_id_shiftrows_mask_bis_0.png" alt="ascad-v2-1 v2_id_shiftrows_mask_bis" width="600"/> | <img src="plots/ascad_v2_1_v2_id_shiftrows_mask_bis_0_zoomed.png" alt="Zoomed v2_id_shiftrows_mask_bis" width="400"/> |
 | ascad-v2-1 | `v2_id_shiftrows_pointer` | 0 | <details><summary>View</summary>16-class Identity target for the destination pointer during ShiftRows.<br><br>``T_SHIFT_ROWS[ perm[byte_index] ]``. Models the physical register holding the destination memory address  during the scatter operation of ShiftRowsWithMasked.</details> | <img src="plots/ascad_v2_1_v2_id_shiftrows_pointer_0.png" alt="ascad-v2-1 v2_id_shiftrows_pointer" width="600"/> | <img src="plots/ascad_v2_1_v2_id_shiftrows_pointer_0_zoomed.png" alt="Zoomed v2_id_shiftrows_pointer" width="400"/> |
 | ascad-v2-1 | `v2_key` | 0 | <details><summary>View</summary>Plain key byte at the AES position consumed by shuffling slot ``byte_index``.<br><br>``key[j]``  where  ``j = perm[byte_index]``.<br><br>The key byte is loaded unprotected from flash/ROM during AddRoundKey r=0 before being scaled into the GF(256) domain via ``gtab``.  Classic first-order DPA target; ``v2_rm_key`` is the masked (GF-scaled) version.</details> | <img src="plots/ascad_v2_1_v2_key_0.png" alt="ascad-v2-1 v2_key" width="600"/> | - |
 | ascad-v2-1 | `v2_lut_idx` | 0 | <details><summary>View</summary>sboxMasked LUT index computed during SubBytes at round 1, slot ``byte_index``.<br><br>``rm * (ptx[j] ^ key[j]) ^ rin``  where  ``j = perm[byte_index]``.<br><br>Computed as ``state[j] ^ state2[j]`` inside the SubBytes loop: the additive masks (masksState) cancel, leaving only the multiplicatively-masked SBI XORed with rin.  This is the value whose hamming weight leaks during the LUT address computation.</details> | <img src="plots/ascad_v2_1_v2_lut_idx_0.png" alt="ascad-v2-1 v2_lut_idx" width="600"/> | <img src="plots/ascad_v2_1_v2_lut_idx_0_zoomed.png" alt="Zoomed v2_lut_idx" width="400"/> |
@@ -138,6 +143,7 @@ This dataset is stored in Zarr format, optimized for chunked and compressed clou
 | ascad-v2-1 | `v2_masked_sbi` | 0 | <details><summary>View</summary>State entering round 1 at slot ``byte_index``: after AddRoundKey r=0.<br><br>``rm * (ptx[j] ^ key[j]) ^ mask[j]``  where  ``j = perm[byte_index]``.<br><br>This is the affine-masked plaintext XOR key value that the round-1 SubBytes call will process.</details> | <img src="plots/ascad_v2_1_v2_masked_sbi_0.png" alt="ascad-v2-1 v2_masked_sbi" width="600"/> | <img src="plots/ascad_v2_1_v2_masked_sbi_0_zoomed.png" alt="Zoomed v2_masked_sbi" width="400"/> |
 | ascad-v2-1 | `v2_mixcolumns_masked` | 0 | <details><summary>View</summary>Output of MixColumns with affine masks still applied.<br><br>``MixColumns(ShiftRows(rm * SBOX(ptx ^ key) ^ mask))[j]`` where ``j = perm[byte_index]``.</details> | <img src="plots/ascad_v2_1_v2_mixcolumns_masked_0.png" alt="ascad-v2-1 v2_mixcolumns_masked" width="600"/> | <img src="plots/ascad_v2_1_v2_mixcolumns_masked_0_zoomed.png" alt="Zoomed v2_mixcolumns_masked" width="400"/> |
 | ascad-v2-1 | `v2_perm` | 0 | <details><summary>View</summary>Shuffling permutation index at slot ``byte_index`` for ASCAD v2.<br><br>Returns ``j = perm[:, byte_index]`` — for each trace the AES byte position (0–15) processed in shuffling slot ``byte_index``.  All other slot-indexed ``v2_*`` targets derive ``j`` via this method.<br><br>**Original-paper label:** ``perm_index[byte_index]`` in the ASCAD v2 HDF5 file.  Derived as:<br><br>  perm[n, i] = G[G[G[G[(15 - i) XOR x0[n]] XOR x1[n]] XOR x2[n]] XOR x3[n]]<br><br>where G = ``_V2_PERM_G`` and x0..x3 are the lower nibbles of mask[:, 0..3].</details> | <img src="plots/ascad_v2_1_v2_perm_0.png" alt="ascad-v2-1 v2_perm" width="600"/> | <img src="plots/ascad_v2_1_v2_perm_0_zoomed.png" alt="Zoomed v2_perm" width="400"/> |
+| ascad-v2-1 | `v2_perm_bis` | 0 | <details><summary>View</summary>Shuffling permutation index for the mask array (state2) at slot ``byte_index``.<br><br>``perm_indices_bis[i] = G4(perm_indices[i], m0..m3)``. Used during ShiftRows to decorrelate the physical access order of the masks  from the physical access order of the state. This is a helper method used  by other bis targets.</details> | <img src="plots/ascad_v2_1_v2_perm_bis_0.png" alt="ascad-v2-1 v2_perm_bis" width="600"/> | <img src="plots/ascad_v2_1_v2_perm_bis_0_zoomed.png" alt="Zoomed v2_perm_bis" width="400"/> |
 | ascad-v2-1 | `v2_ptx` | 0 | <details><summary>View</summary>Plaintext byte at the AES position consumed by shuffling slot ``byte_index``.<br><br>``ptx[j]``  where  ``j = perm[byte_index]``.<br><br>The byte value loaded from the plaintext register before ``Map_in_G`` scales it into the GF(256) multiplicative domain.  Classic first-order DPA target; ``v2_rm_ptx`` is the masked version after Map_in_G.</details> | <img src="plots/ascad_v2_1_v2_ptx_0.png" alt="ascad-v2-1 v2_ptx" width="600"/> | - |
 | ascad-v2-1 | `v2_raw_out` | 0 | <details><summary>View</summary>SubBytes ``raw_out`` at round 1, slot ``byte_index``: the sboxMasked LUT output.<br><br>``rm * SBOX(ptx[j] ^ key[j]) ^ rout``  where  ``j = perm[byte_index]``.<br><br>This is ``sboxMasked[lut_idx]`` — the value read from the firmware's masked S-Box LUT before it is XORed with ``state2[j]`` (masksState). It sits between :meth:`v2_lut_idx` (the LUT address) and :meth:`v2_sbo_mid` (the value written back into ``state[j]``).<br><br>**Original-paper label:** ``sbox_masked[byte_index]`` in the ASCAD v2 HDF5 file and the NCC Group ML-104 blog 34-task model.</details> | <img src="plots/ascad_v2_1_v2_raw_out_0.png" alt="ascad-v2-1 v2_raw_out" width="600"/> | <img src="plots/ascad_v2_1_v2_raw_out_0_zoomed.png" alt="Zoomed v2_raw_out" width="400"/> |
 | ascad-v2-1 | `v2_raw_out_direct` | 0 | <details><summary>View</summary>SubBytes ``raw_out`` at round 1 indexed directly by AES byte position.<br><br>``rm * SBOX(ptx[i] ^ key[i]) ^ rout``  where  ``i = byte_index`` (no perm).<br><br>Unlike :meth:`v2_raw_out`, the shuffle permutation is **not** applied — ``byte_index`` maps directly to the AES state byte position.  This is the same formula as :meth:`v2_raw_out` but over the identity byte ordering, making it practical as an un-permuted SNR or model target.<br><br>**Original-paper label:** ``sbox_masked_with_perm[byte_index]`` in the ASCAD v2 HDF5 file and the NCC Group ML-104 blog 18-task model (``RMmSBOxROUT`` in scandal/crypto.py).</details> | <img src="plots/ascad_v2_1_v2_raw_out_direct_0.png" alt="ascad-v2-1 v2_raw_out_direct" width="600"/> | - |